Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out

The aggressive scaling of nanometer CMOS technology nodes and the integration of low-k dielectrics introduces novel reliability phenomena that progressively degrade the electrical characteristics of copper interconnects. These effects impact the performance of designs gradually rather than abruptly, leading to timing violations in several timing-critical paths and thus shortening the system’s lifetime. Therefore, the need for design methodologies predicting the impact of such phenomena is emerging. This paper presents a case study for a dominating interconnect reliability effect, Electro-migration, based on an MPSoC platform with two LEON3 SPARC processors as kernels. The proposed flow studies the impact of Electro-migration on the timing-critical paths of the design and estimates the system’s lifetime due to this effect. The presented case study may be used as a guide to estimate the impact of Electro-migration in the performance of complex, MP-SOC designs, based on a proposed analysis framework, which can be extended to the study of relevant interconnect reliability phenomena.